WO 2007/016552 A1 - Amplifier With Active Post-distortion Linearization - The Lens

Abstract

An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.

Claims

An integrated circuit comprising: a first transistor electrically coupled to an inductor and operative to receive and amplify an input signal; a second transistor electrically coupled to the first transistor and operative to generate an intermediate signal and to provide an output signal; and a third transistor electrically coupled to the second transistor and operative to receive the intermediate signal and generate distortion components used to cancel a distortion component generated by the first transistor.
The integrated circuit of claim 1, wherein the first and second transistors are coupled as a cascode pair.
The integrated circuit of claim 1, wherein the third transistor is operative to generate distortion components used to cancel third order distortion component generated by the first transistor.
The integrated circuit of claim 1, further comprising: a fourth transistor electrically coupled to the second and third transistors and operative to provide load isolation.
The integrated circuit of claim 1, wherein the third transistor has a drain electrically coupled to a drain of the second transistor.
The integrated circuit of claim 1, wherein the third transistor has a drain electrically coupled to a drain of the first transistor.
The integrated circuit of claim 1, wherein the first, second, and third transistors have first, second, and third gains, respectively, wherein the first and second gains are related by a first factor, and wherein the first and third gains are related by a second factor.
The integrated circuit of claim 7, wherein the second factor is selected to reduce gain loss, and wherein the first factor is selected to cancel the distortion component generated by the first transistor.
The integrated circuit of claim 7, wherein the second factor is greater than one, and wherein the third gain is a fraction of the first gain.
The integrated circuit of claim 1, wherein the first, second, and third transistors are N-channel field effect transistors (N-FETs).
The integrated circuit of claim 1, wherein the first, second, and third transistors are P-channel field effect transistors (P-FETs).
The integrated circuit of claim 1, wherein the first, second, and third transistors are bipolar junction transistors (BJTs).
The integrated circuit of claim 1, wherein the first, second, and third transistors form a low noise amplifier (LNA).
The integrated circuit of claim 1 , further comprising: a gain control circuit electrically coupled to the first and second transistors and operative to provide gain control for an amplifier formed by the first, second, and third transistors.
The integrated circuit of claim 14, wherein the gain control circuit comprises a fourth transistor electrically coupled to the first transistor; and a capacitor electrically coupled between the fourth transistor and the second transistor.
The integrated circuit of claim 14, wherein the gain control circuit comprises a fourth transistor electrically coupled to the first transistor; and at least one resistor electrically coupled between the fourth transistor and the second transistor.
The integrated circuit of claim 1, wherein the input signal is a Code Division Multiple Access (CDMA) signal.
An amplifier comprising: an inductor operative to provide source degeneration; a first transistor having a source electrically coupled to the inductor and a gate receiving an input signal, the first transistor operative to provide signal amplification; a second transistor having a drain providing an output signal and a source electrically coupled to a drain of the first transistor, the second transistor operative to generate an intermediate signal; and a third transistor having a gate electrically coupled to the source of the second transistor, the third transistor operative to receive the intermediate signal and generate distortion components used to cancel a distortion component generated by the first transistor.
The amplifier of claim 18 , further comprising: a fourth transistor having a source electrically coupled to a drain of the third transistor and a drain electrically coupled to the drain of the second transistor.
An apparatus comprising: means for amplifying an input signal to generate a first signal having a desired component and a distortion component; means for generating a second signal having distortion components used to cancel the distortion component generated by the amplifying means; and means for combining the first and second signals to generate an output signal having the distortion component generated by the amplifying means canceled.
The apparatus of claim 20, wherein the distortion component generated by the amplifying means is a third order distortion component.
The apparatus of claim 20, further comprising: means for controlling gain of the output signal.
A receiver for a wireless device, comprising: a low noise amplifier (LNA) comprising an inductor operative to provide source degeneration, a first transistor having a source electrically coupled to the inductor and operative to provide signal amplification, a second transistor having a source electrically coupled to a drain of the first transistor and operative to generate an intermediate signal, and a third transistor having a gate electrically coupled to the source of the second transistor, the third transistor operative to receive the intermediate signal and generate distortion components used to cancel a distortion component generated by the first transistor; an input impedance matching circuit electrically coupled to a gate of the first transistor and receiving an input signal for the LNA; and an output impedance matching circuit electrically coupled to a drain of the second transistor and providing an output signal for the LNA.
The receiver of claim 23, wherein the LNA further comprises a fourth transistor having a source electrically coupled to a drain of the third transistor and a drain electrically coupled to the drain of the second transistor.
The receiver of claim 23, wherein the LNA further comprises a gain control circuit electrically coupled to the first and second transistors and operative to provide gain control for the LNA.