Electronic Interconnects And Devices With Topological Surface States And Methods For Fabricating Same

  *US09331020B2*
  US009331020B2                                 
(12)United States Patent(10)Patent No.: US 9,331,020 B2
 Yazdani et al. (45) Date of Patent:May  3, 2016

(54)Electronic interconnects and devices with topological surface states and methods for fabricating same 
    
(76)Inventors: Ali Yazdani,  Princeton, NJ (US); 
  N. Phuan Ong,  Belle Mead, NJ (US); 
  Robert J. Cava,  Princeton, NJ (US) 
(*)Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 930 days. 
(21)Appl. No.: 13/039,762 
(22)Filed: Mar.  3, 2011 
(65)Prior Publication Data 
 US 2012/0161209 A1 Jun.  28, 2012 
 Related U.S. Patent Documents 
(60)Provisional application No. 61/368,552, filed on Jul.  28, 2010.
 
Jan.  1, 2013 H 01 L 23 53209 F I May  3, 2016 US B H C Jan.  1, 2013 C 22 C 28 00 L I May  3, 2016 US B H C Jan.  1, 2013 C 22 C 30 00 L I May  3, 2016 US B H C Jan.  1, 2013 H 01 L 21 76838 L I May  3, 2016 US B H C Jan.  1, 2013 H 01 L 23 53271 L I May  3, 2016 US B H C Jan.  1, 2013 H 01 L 29 78 L I May  3, 2016 US B H C Jan.  1, 2013 H 01 L 29 78681 L I May  3, 2016 US B H C Jan.  1, 2013 H 01 L 2924 0002 L A May  3, 2016 US B H C Jan.  1, 2013 H 01 L 2924 01051 L A May  3, 2016 US B H C Jan.  15, 2015 Y 10 T 29 49204 L A May  3, 2016 US B H C 1 1 Jan.  1, 2013 H 01 L 2924 0002 L A May  3, 2016 US B H C 2 Jan.  1, 2013 H 01 L 2924 00 L A May  3, 2016 US B H C
(51)Int. Cl. H01L 029/76 (20060101); H01L 023/532 (20060101); H01L 029/786 (20060101); H01L 021/768 (20060101); C22C 028/00 (20060101); C22C 030/00 (20060101); H01L 029/78 (20060101)
(58)Field of Search  257/288; 136/201, 205, 212, 227, 236.1

 
(56)References Cited
 
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     * cited by examiner
 
     Primary Examiner —Zandra Smith
     Assistant Examiner —John M Parker
     Art Unit — 2816
     Exemplary claim number — 1
 
(74)Attorney, Agent, or Firm — Meagher Emanuel Laks Goldberg & Liao, LLP.

(57)

Abstract

An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.
21 Claims, 5 Drawing Sheets, and 5 Figures


CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Application No. 61/368,552, filed on Jul. 28, 2010, which is incorporated herein by reference as if fully set forth.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Grants #DMR-0704314 and DMR-0819860 awarded by the National Science Foundation; Grant #N00014-07-1-0348 awarded by the Office of Naval Research; Grant #DE-FG02-07ER46419 awarded by the Department of Energy and Grant #W911NF-07-1-0125 awarded by the Army Research Office. The government has certain rights in this invention.

FIELD OF INVENTION

[0003] This is directed toward electronic device fabrication.

BACKGROUND

[0004] One of the challenges in reducing the size of electronic devices is associated with the resistance of the metallic interconnects that are used in today's integrated circuits. Current technology relies on the use of metal interconnects exhibiting normal electrical resistance. These interconnects show an increase in their resistance when fabricated with a dimension below about 20 nm. A significant contribution to this resistance is associated with scattering of charge carriers at the surface of the interconnects. This surface contribution naturally becomes more significant as the size of the interconnects decreases. This is because as the size decreases a larger fraction of the charge carriers are at or near a surface.

SUMMARY

[0005] An interconnect with enhanced immunity of electrical conductivity to defects is described. The interconnect is fabricated using a material with charge carriers having topological surface states. A method for fabricating such interconnects is also described. An integrated circuit including such interconnects and a gated electronic device including a material with charge carriers having topological surface states are also described.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIGS. 1a and 1b illustrate properties of topological surface states.
[0007] FIG. 2 shows an embodiment of an electronic circuit with multi-level interconnects.
[0008] FIG. 3 shows an embodiment of a gated electronic modulation device.
[0009] FIG. 4 shows plots of properties of the example gated electronic modulation device, and
[0010] FIG. 5 is a graph showing relationship between surface states and the bulk portion.

DETAILED DESCRIPTION

[0011] Recently, materials have been fabricated in which charge carriers, such as electrons, move in topological surface states. What distinguishes these states from previously known charge carrier states is that topological surface states depend on the spin of the charge carrier, in addition to its charge and mass. Like charge and mass, spin is an inherent property of a charge carrier such as an electron. It has units of angular momentum and may be described using quantum-mechanical vector concepts. In a topological surface state an interaction between a spin vector and a momentum vector of a charge carrier results in these two vectors being locked perpendicular to each other. In the case of electrons, this interaction is related to the spin-orbit interaction of the electrons in the atoms making up the material. Electrical conduction involving topological surface states contrasts sharply with traditional practical electrical conduction, in which only the momentum, not the spin, plays a role.
[0012] The existence of topological surface states has been demonstrated, and their properties characterized, using various techniques, such as angle-resolved photoemission spectroscopy (ARPES), scanning tunneling microscopy, Shubnikov-de Haas oscillations and weak-field Hall effect. Topological surface states are characterized by energy bands that are distinguishable from those of the bulk material. Spin-orbit or spin-momentum interaction needs to be relatively strong for topological surface states to exist. For example, heavy elements, such as Bi and Sb, have such relatively strong interactions, and materials incorporating such elements may be expected to exhibit topological surface states. Topological surface states have been observed in stoichiometric and non-stoichiometric substances. They have been observed in substances including elements from groups 13, 14, 15, and 16 of the periodic table. They have been also observed in solid solution alloys.
[0013] A property that distinguishes topological surface states from ordinary surface states, making them potentially advantageous for electronics applications at nanometer dimensions, is their immunity to backscattering from impurities and crystallographic defects which are present on all solid surfaces. This property gives rise to enhanced transmission of carriers in these states through energy barriers, compared to such transmission of other surface states. Impurities or defects in materials may give rise to such barriers. This enhanced transmission may be advantageous when significant surface conduction is unavoidable. The effect is illustrated in FIGS. 1a and 1b. FIG. 1a illustrates scattering by an impurity 15a of electrons 10a in a classical state, depending only on momentum. The electrons are scattered more or less uniformly in every direction, as depicted by the arrows 20a and 25a, which are all of essentially the same length. Arrow 20a indicates the particular case of 180° backscattering. FIG. 1b, by contrast, illustrates scattering by an impurity 15b of electrons 10b in a topological surface state, characterized by momentum and spin locked together. In this case, electron scattering is not uniform but depends on direction, as indicated by the varying lengths of arrows 20b and 25b. The most probable direction for electron scattering is the forward direction. Most noteworthy is the absence of scattering in the 180° backscattering direction, as shown by a missing arrow at position 20b.
[0014] The existence of topological surface states with enhanced mobility and absence of backscattering has been demonstrated experimentally. As one example, electron mobility exceeding 9000 cm2/V-s in topological surface states has been measured by the inventors in Bi2Te3. The electron mobility of electrons in the bulk of the same samples has been estimated as being lower than the topological surface state mobility by about a factor of 12. Other measurements and observations in elemental antimony (Sb) by the inventors confirm that this mobility is occurring in topological surface states and that charge carriers in these states are protected against backscattering from defects. This protection from backscattering accounts, at least in part, for the relatively high surface mobility.
[0015] In another example, experiments using scanning tunneling microscopy (STM) on Bi1-xSbx (0.07≦x≦1) and Sb have demonstrated that charge carriers in topological surface states are indeed forbidden from making a transition between a state with forward momentum and a state with backward momentum, as illustrated in FIG. 1b. Protection from 180° backscattering is a direct consequence of the nature of topological surface states, which requires the backscattering to be accompanied by flipping of an electron's spin. In the absence of any magnetic impurity in the material, the topological surface state electrons have coupled spin angular momentum and crystal momentum and are said to be topologically protected.
[0016] Topological surface states, when compared to ordinary surface states, also possess the ability to transmit through a crystallographic barrier such as atomic steps with enhanced probability. This property has been demonstrated experimentally by the inventors using STM experiments on domains of crystalline Sb. The crystalline domains were configured to support current flow parallel to a [111] crystallographic surface. The results of these experiments demonstrate that crystalline steps do not necessarily confine carriers in topological surface states, unlike in typical metals (such as Au, Ag, and Cu), in which steps can confine carriers in non-topological surface states. Experiments estimate the transmission of surface electrons through crystalline steps in Sb to be 35%. In contrast, similar experiments on surface states of Cu, Au, and Ag show no such transmission.
[0017] Calculations indicate that similar protection against backscattering and enhanced surface mobilities should occur in topological surface states in the following materials and families of materials: Bi1-xSbx, where 0.07≦x≦1; Bi(2-2x)Sb2xSe(3-3y)Te3y where 0≦x≦1 and 0≦y≦1; TlBiSe2-2xTe2x, where 0≦x≦1; TlSbSe2-2xTe2x, where 0≦x≦1; GeBi2Te4; GeBi4Te7; a heavy metal half Heusler phase with 18 electrons per formula unit such as LuPtSb; and HgTe—CdTe layered structures.
[0018] ARPES measurements have observed signatures of topological surface states for a number of compounds with a bulk gap, the so-called topological insulators (such as Bi1-xSbx (x>0.07), Bi2Se3, Bi2Te3, Bi1-xSe3-xTex, Bi2-xSb3-xTex, TlBiTe2, TlBiSe2, GeBi2Te4, and GeBi4Te7), as well as on the surface of the semimetal Sb8−. It is has been theoretically predicted that heavy metal half Heusler phases with 18 electrons per formula unit (such as LuPtSb), as well as compounds that are composed of Tl (such as TlSbSe2), may also posses topological surface states. Since most of the compounds discovered to date show a bulk band gap in ARPES measurements, these compounds are often referred to as topological insulators. The presence of defects and dopants in these compounds, however, may give rise to non-zero electrical conduction under most circumstances.
[0019] Materials with topological surface states fabricated in nanometer-scale circuits may show much superior performance as interconnects and achieve significantly lower resistance compared to Cu and other metals now conventionally used for interconnects. The inventors' demonstration that the surface state electrons are robust against scattering from defects and crystallographic imperfection illustrates this utility. In general, both metallic and semiconducting materials with topological surface states can be used for applications disclosed below.
[0020] FIG. 2 shows an example, not to be construed as limiting, of a cross-section of an integrated circuit device with interconnects fabricated from a material exhibiting electrical conduction in topological surface states. Five levels of such interconnects are shown, labeled M1, M2, M3, M4 and M5. Some of these conducting interconnects provide an electrically conducting path between devices in a plurality of devices 20. Others provide a conducting path between devices 20 and other components not shown. Connections between levels are made through vias V1, V2, V3, and V4 in dielectric layers separating the interconnect layers M1, M2, M3, M4 and M5.
[0021] In one embodiment, not to be considered limiting, interconnects such as those shown in FIG. 2 may be fabricated by fabricating a film of material with charge carriers having topological surface states and patterning the film to form the interconnect, using patterning techniques known in the art. A variety of methods may be used to fabricate materials with topological surface states. These include various methods for growing single crystals, molecular-beam-epitaxy techniques for creating thin films, and various other methods for creating nano-ribbons or small wires.
[0022] As an example of the use of crystal growth, demonstrated by the inventors, Bi1-xSbx single crystals may be grown by melting stoichiometric mixtures of elemental Bi (99.999%) and Sb (99.999%) in 4-mm inner diameter quartz tubes. The samples may be cooled over a period of two days, from 650 to 260° C., and then annealed for a week at 260° C. A single crystal of antimony from a boule grown by the modified Bridgman method may be used for various applications. Before the growth, high-purity antimony (99.999%) may be sealed in a vacuum quartz tube and heated to 700° C. The crystal growth process has been found to take about a day at a slow rate of cooling from 700 to 500° C. The boule may then be kept at 500° C. for annealing over five days. The boule may then be furnace-cooled to room temperature (25° C.).
[0023] The behavior of topological surface states may be sensitive to the position of the chemical potential (Fermi level) within the band structure of the host material. In the preparation of a material having topological surface states, dopants may be introduced into the material to move the chemical potential to a desired position, within the bulk band gap for example. As a specific example, a relatively small concentration of calcium atoms has been introduced into BiSe3 to make it more p-type.
[0024] FIGS. 3 and 4 show another example, with actual experimental results, of a device based on materials exhibiting topological surface states. It is a gated device, in which the resistivity of a material can be varied by using an applied potential to change the relative proportion of electrons moving in traditional states and in topological surface states. This device may therefore be operated as a modulation device. Modulation devices are useful in a large variety of applications such as wireless communications. As shown in FIG. 3, a small crystal of Bi2Te3 30, a material with charge carriers having topological surface states, is connected to electrodes 35 and supported on a doped silicon substrate (not visible), that acts as a gate material. A potential may be applied to this gate. Between the silicon gate and topological surface state material is an insulating layer (not visible) that may act as a gate dielectric. As shown in FIG. 4, resistance (R) of the structure is dependent on both temperature T and applied gate potential Vg. At a fixed temperature the resistance may be modulated by varying the gate potential Vg. The device may therefore be operated as a current modulator.
[0025] It may be deduced from the data of FIG. 4 that the modulation of the resistivity by the gate potential Vg occurs because varying Vg changes the proportion of charged carrier transport via the topological surface states relative to charged carrier transport via bulk states in the same material. This occurs, in turn, because increasing Vg moves the Fermi level (chemical potential) of the carriers from the bulk gap to the conduction band.
[0026] While several embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the functions and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the present embodiments. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings herein is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, the embodiments disclosed may be practiced otherwise than as specifically described and claimed. The present embodiments are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present embodiments.
(57)

Claims

1. An interconnect comprising a material that is purified and crystalized to form an essentially insulating bulk portion having topological surface states occupied with charge carriers, the charge carriers having a spin vector and a momentum vector that are locked in a perpendicular relationship, the topological surface states and the essentially insulating bulk portion each having an electrical mobility, the electrical mobility of the topological surface states being at least 12 times greater than the electrical mobility of the essentially insulating bulk portion.
2. The interconnect of claim 1, wherein the material has a mobility for the charge carriers of at least 9000 centimeter-squared per volt-second (cm2/V-s).
3. The interconnect of claim 1, wherein the material comprises a non-stoichiometric material.
4. The interconnect of claim 1, wherein the material comprises an element from column 15 of the periodic table.
5. The interconnect of claim 1, wherein the material comprises an element from column 16 of the periodic table.
6. The interconnect of claim 1, wherein the material comprises an element from column 13 of the periodic table.
7. The interconnect of claim 1, wherein the material comprises an element from column 14 of the periodic table.
8. The interconnect of claim 1, wherein the material comprises a solid solution alloy.
9. The interconnect of claim 1, wherein the material has an atomic composition Bi1-xSbx, where 0.07≦x≦1.
10. The interconnect of claim 1, wherein the material has an atomic composition Bi(2-2x)Sb2xSe(3-3y)Te3y where 0≦x≦1 and 0≦y≦1.
11. The interconnect of claim 1, wherein the material has an atomic composition TlBiSe2-2xTe2x, where 0≦x≦1.
12. The interconnect of claim 1, wherein the material has an atomic composition TlSbSe2-2xTe2x, where 0≦x≦1.
13. The interconnect of claim 1, wherein the material has an atomic composition GeBi2Te4.
14. The interconnect of claim 1, wherein the material has an atomic composition GeBi4Te7.
15. The interconnect of claim 1, wherein the material comprises a heavy metal half Heusler phase with 18 electrons per formula unit.
16. The interconnect of claim 1, comprising LuPtSb.
17. The interconnect of claim 1, wherein the material comprises an HgTe—CdTe layered structure.
18. The interconnect of claim 1, wherein the material comprises domains of crystalline antimony, the domains configured to support current flow parallel to a [111] crystallographic surface.
19. An integrated circuit comprising:
a plurality of devices; and
an interconnect providing an electrically conducting path between devices, the interconnect comprising a material that is purified and crystalized to form an essentially insulating bulk portion having topological surface states occupied with charge carriers, the charge carriers having a spin vector and a momentum vector that are locked in a perpendicular relationship, the topological surface states and the essentially insulating bulk portion each having an electrical mobility, the electrical mobility of the topological surface states being at least 12 times greater than the electrical mobility of the essentially insulating bulk portion.
20. A gated electronic device, comprising:
a material that is purified and crystalized to form an essentially insulating bulk portion having topological surface states occupied with charge carriers, the charge carriers having a spin vector and a momentum vector that are locked in a perpendicular relationship, the topological surface states and the essentially insulating bulk portion each having an electrical mobility, the electrical mobility of the topological surface states being at least 12 times greater than the electrical mobility of the essentially insulating bulk portion;
an insulator situated on the material; and
a gate material situated on the insulator;
wherein applying a potential to the gate material modulates a current flowing in the topological surface states of the material.
21. The device of claim 20, configured such that the applying of the potential to the gate material changes the proportion of charged carrier transport via the topological surface states relative to charged carrier transport via bulk states.
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