{"search_session":{},"preferences":{"l":"en","queryLanguage":"en"},"patentId":"106-190-502-311-647","frontPageModel":{"patentViewModel":{"ref":{"entityRefId":"106-190-502-311-647","entityRefType":"PATENT"},"entityMetadata":{"linkedIds":{"empty":true},"tags":[],"collections":[{"id":8901,"type":"PATENT","title":"University of Michigan Patent Portfolio","description":"","access":"OPEN_ACCESS","displayAvatar":true,"attested":false,"itemCount":14369,"tags":[],"user":{"id":91044780,"username":"Cambialens","firstName":"","lastName":"","created":"2015-05-04T00:55:26.000Z","displayName":"Cambialens","preferences":"{\"usage\":\"public\",\"beta\":false}","accountType":"PERSONAL","isOauthOnly":false},"notes":[{"id":8216,"type":"COLLECTION","user":{"id":91044780,"username":"Cambialens","firstName":"","lastName":"","created":"2015-05-04T00:55:26.000Z","displayName":"Cambialens","preferences":"{\"usage\":\"public\",\"beta\":false}","accountType":"PERSONAL","isOauthOnly":false},"text":"
Search Applicants and Owners= \"Univ Michigan\", \" Michigan Univ\", \" Univ Michigan NOT state NOT tech NOT Eastern\", \"Univ Michigan NOT technological\", \" Univ Michigan NOT Western\"
Select more for logical variants
Add to collection
Total patent : 14104
Search Applicants and Owners= \"Univ Michigan\", \" Michigan Univ\", \" Univ Michigan NOT state NOT tech NOT Eastern\", \"Univ Michigan NOT technological\", \" Univ Michigan NOT Western\"
Select more for logical variants
Add to collection
Total patent : 14104
a first electrode being a source of ions;\n
a planar doped silicon second electrode; and\n
a non-crystalline silicon layer having a resistance and being positioned to receive the ions from the first electrode wherein the ions are driven into the non-crystalline silicon layer to form a conducting filament from the first electrode to the second electrode to alter the resistance of the non-crystalline silicon layer when an electrical potential between the electrodes is greater than a first threshold electrical potential."],"number":1,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the non-volatile solid state resistive switching device is a memory device."],"number":2,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the resistance of the non-crystalline silicon layer is dependent upon a polarity of the electrical potential."],"number":3,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the resistance of the non-crystalline silicon layer is independent of a polarity of the electrical potential."],"number":4,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein at least a portion of the ions forming the conducting filament are removed from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer when the electrical potential is less than a second threshold electrical potential."],"number":5,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 5 wherein the resistance of the non-crystalline silicon layer is substantially unaltered when the electrical potential is less than the first threshold electrical potential and greater than the second threshold electrical potential."],"number":6,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 5 wherein the resistance of the non-crystalline silicon layer is substantially unaltered in an absence of the electrical potential."],"number":7,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the non-crystalline silicon layer comprises amorphous silicon."],"number":8,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 further comprising a third electrode being adjacent to the second electrode for reducing a resistance presented to the non-crystalline silicon layer wherein the second electrode is sandwiched between the non-crystalline silicon layer and the third electrode."],"number":9,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the first electrode comprises a metal."],"number":10,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 10 wherein the metal comprises at least one of silver, gold, nickel, aluminum, chromium, iron, manganese, tungsten, vanadium and cobalt."],"number":11,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein an area of interface between the non-crystalline silicon layer and the electrodes is equal to or less than 2500 nm2."],"number":12,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the second electrode has a resistivity equal to or less than 0.01 Ω·cm."],"number":13,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 13 wherein the second electrode has a resistivity equal to or less than 0.005 Ω·cm."],"number":14,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 further comprising an insulative layer sandwiched between the first electrode and the non-crystalline silicon layer for defining an active area of the device."],"number":15,"annotation":false,"claim":true,"title":false},{"lines":["A silicon based memory device having a cell size less than or equal to 0.01 μm2."],"number":16,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 16 wherein the cell size is less than 0.003 μm2."],"number":17,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 1 wherein the second electrode is a p-type silicon electrode."],"number":18,"annotation":false,"claim":true,"title":false},{"lines":["A memory system comprising:\n
an array of non-volatile solid state resistive switching devices wherein each switching device of the array includes\n"],"number":19,"annotation":false,"claim":true,"title":false},{"lines":["The system of claim 19 wherein the electrodes form a crossbar structure."],"number":20,"annotation":false,"claim":true,"title":false},{"lines":["The system of claim 19 wherein at least a portion of the ions forming the conducting filament are removed from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer when the electrical potential is less than a second threshold electrical potential."],"number":21,"annotation":false,"claim":true,"title":false},{"lines":["The system of claim 21 wherein the resistance of the non-crystalline silicon layer is substantially unaltered when the electrical potential is less than the first threshold electrical potential and greater than the second threshold electrical potential."],"number":22,"annotation":false,"claim":true,"title":false},{"lines":["The system of claim 19 wherein each switching device of the array further includes a third electrode being adjacent to the second electrode for reducing a resistance presented to the non-crystalline silicon layer."],"number":23,"annotation":false,"claim":true,"title":false},{"lines":["A memory system comprising:\n(i) a first electrode being a source of ions,\n(ii) a planar doped silicon second electrode, and\n(iii) a non-crystalline silicon layer having a resistance and being positioned to receive the ions from the first electrode wherein the ions are driven into the non-crystalline silicon layer to form a conducting filament from the first electrode to the second electrode to alter the resistance of the non-crystalline silicon layer when an electrical potential between the electrodes is greater than a first threshold electrical potential.\n
a plurality of metal electrodes being a source of ions;\n
a plurality of planar doped silicon electrodes wherein the plurality of metal electrodes and planar doped silicon electrodes form a crossbar structure; and\n
a non-crystalline silicon layer having a resistance and being positioned to receive the ions from the metal electrodes wherein the ions from one of the metal electrodes are driven into a portion of the non-crystalline silicon layer to form a conducting filament from the one metal electrode to one of the plurality of planar doped silicon electrodes adjacent to the one metal electrode to alter the resistance of the portion of the non-crystalline silicon layer when an electrical potential between the one metal electrode and the one planar doped silicon electrode is greater than a first threshold electrical potential."],"number":24,"annotation":false,"claim":true,"title":false},{"lines":["The device of claim 24 wherein at least a portion of the ions forming the conducting filament are removed from the portion of the non-crystalline silicon layer to further alter the resistance of the portion of the non-crystalline silicon layer when the electrical potential is less than a second threshold electrical potential."],"number":25,"annotation":false,"claim":true,"title":false}]}},"filters":{"npl":[],"notNpl":[],"applicant":[],"notApplicant":[],"inventor":[],"notInventor":[],"owner":[],"notOwner":[],"tags":[],"dates":[],"types":[],"notTypes":[],"j":[],"notJ":[],"fj":[],"notFj":[],"classIpcr":[],"notClassIpcr":[],"classNat":[],"notClassNat":[],"classCpc":[],"notClassCpc":[],"so":[],"notSo":[],"sat":[]},"sequenceFilters":{"s":"SEQIDNO","d":"ASCENDING","p":0,"n":10,"sp":[],"si":[],"len":[],"t":[],"loc":[]}}