WO 2017/123902 A1 - Cryptographic Asic Including Circuitry-encoded Transformation Function - The Lens

Cryptographic Asic Including Circuitry-encoded Transformation Function

Published: Jul 20, 2017
Earliest Priority: Jan 15 2016
Family: 5
Cited Works: 0
Cited by: 4
Cites: 7
Additional Info: Full text

Abstract

A transform-enabled integrated circuit for use in cryptographic proof-of-work systems is provided. The transform-enabled integrated circuit includes a transformation block embedded among other circuitry components within the cryptographic datapath of the transform-enabled integrated circuit. The transformation block may be configured at a time subsequent to the manufacture of the integrated circuit to embody as circuitry any one of a plurality of mathematical transformation functions, thus enabling a user to systemically modify the results of cryptographic operations performed by the integrated circuit while retaining the high performance and efficiency characteristics of application specific integrated circuits. Embodiments of the technology disclosed herein provides an hereto unachievable level of flexibility in the deployment of application-specific integrated circuits within proof-of-work verification systems, such as private block chain systems, public block chain systems, digital rights management, secure token and other cryptography-related fields.

Claims

A cryptographic integrated circuit, comprising:
a transformation block comprising a set of electronic circuitry integrated into a datapath circuitry of the cryptographic integrated circuit, and
programmable at a time subsequent to the manufacture of the integrated circuit to perform a transform operation on data received from datapath circuitry prior to the transformation block;
a programming circuit communicatively coupling the transformation block and a configuration interface;
wherein the integrated circuit is implemented within a cryptographic circuit, and a user may program the transformation block through the configuration interface such that the transformation block is configured in accordance with a configuration key.
The cryptographic integrated circuit of claim 1, wherein the
transformation block comprises a configuration key programmable by the user and is configured as datapath circuitry capable of operating at the same speed as other circuitry along the integrated circuits cryptographic datapath.
The cryptographic integrated circuit of claim 2, the datapath circuity further comprising a hashing block configured to apply a hashing algorithm determined in accordance with a cryptographic standard specified by a proof-of- work protocol.
The cryptographic integrated circuit of claim 2, further comprising a permanent and indelible mechanism to embody the key entered by the user as physical circuitry on the integrated circuits datapath.
The cryptographic integrated circuit of claim 2, further comprising a nonpermanent mechanism to embody the key entered by the user as physical circuitry on the integrated circuits datapath.
The cryptographic integrated circuit of claim 2, wherein the
transformation block is configured to implement a direct bit inversion scheme.
The cryptographic integrated circuit of claim 2, wherein the
transformation block may configured to implement a bit transposition scheme.
The cryptographic integrated circuit of claim 2, the integrated circuit designed and fabricated to implement a secure hashing algorithm.
The cryptographic integrated circuit of claim 1, the datapath circuity further comprising a first hashing block configured to apply a first hashing algorithm determined in accordance with a cryptographic standard specified by a proof-of-work protocol, and a second hashing block configured to subsequently apply a second hashing algorithm determined in accordance with a cryptographic standard specified by a proof-of-work protocol.
The cryptographic integrated circuit of claim 9, the transformation block being located before the first hashing block such that an output of the transformation block is an input to the first hashing block.
The cryptographic integrated circuit of claim 9, the transformation block being located between the first and second hashing blocks such that an output of the first hashing block is an input to the transformation block and an output of the transformation block is an input to the second hashing block.
The cryptographic integrated circuit of claim 9, further comprising a second transformation block.
The cryptographic integrated circuit of claim 1, the datapath circuitry comprising a plurality of cryptographic cores, each cryptographic core of the plurality of cryptographic cores comprising a first hashing block.
The cryptographic integrated circuit of claim 13, each cryptographic core of the plurality of cryptographic cores comprising a transformation block.
The cryptographic integrated circuit of claim 1, the datapath circuitry comprising a plurality of cryptographic cores, each cryptographic core of the plurality of cryptographic cores comprising two hashing blocks connected sequentially such that an output from a first hashing block is an input to a second hashing block either directly or after passing through additional circuitry blocks.
The cryptographic integrated circuit of claim IS, the first transformation block being located before the first hashing block such mat an output of the transformation block is an input to the first hashing block and the second transformation block being located before the second hashing block such that an output from the first hashing core is an input to the second transformation block, and an output from the second transformation block is an input to the second hashing block.
The cryptographic integrated circuit of claim IS, both transformation blocks being located before the first hashing block such that the combined output from both transformation blocks is an input to the first hashing block.
The cryptographic integrated circuit of claim IS, both transformation blocks being located after the first hashing block such than an output from the first hashing block is an input to the transformation blocks and before the second hashing block such that the combined output from both transformation blocks is an input to the second hashing block.
The cryptographic integrated circuit of claim IS, wherein a first transformation block is shared by each cryptographic core of the plurality of cryptographic cores and a second transformation block is shared by each cryptographic core of the plurality of cryptographic cores.
The cryptographic integrated circuit of claim 1 , further comprising a lock fuse disposed within the programming circuit, wherein the transformation block is inaccessible when the lock fuse is disabled.