Verification System For Secure Transmission In A Distributed Processing Network

  • Published: May 19, 2016
  • Earliest Priority: Aug 22 2014
  • Family: 9
  • Cited Works: 0
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  • Additional Info: Full text

A verification system, includes: an arithmetic/logic unit ("ALU") to perform one or more mathematical operations and compare selected variables; a register to hold a value from a comparison of selected variables performed by the ALU; an instruction decoder to provide read and write commands to memory; an address bus to provide an address to memory for a read or write operation; and a data bus to provide or access data for a write or read operation to or from memory, wherein the ALU generates and provides a recipient identifier to a target computational device, the recipient identifier being related to an identity of the target computational device and/or a target device human operator, and write the recipient identifier to memory in response to a write command issued by the instruction decoder and, as a part of a transaction, the ALU receives, from a user computational device of a first user, the recipient identifier and a credential of the first user and/or user computational device, compares each of the recipient identifier and credential against one or more stored values, and, when each of the comparisons match, causes information provider system to provide restricted information to the target computational device to enable the target computational device to perform an operation.


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