Mechanism For Compensating For Gate Leakage In A Memory

  • Published: Apr 7, 2009
  • Earliest Priority: Jul 02 2007
  • Family: 1
  • Cited Works: 0
  • Cited by: 2
  • Cites: 2
  • Additional Info: Full text
Abstract

A memory is disclosed having one or more logic level reinforcement circuits (LLRC's) coupled to each wordline. Each LLRC has an input and an output, both of which are coupled to a corresponding wordline. The LLRC senses a present logic level on the wordline. If the present logic level is a first logic level, then the LLRC outputs a first logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. If the present logic level is the second logic level, then the LLRC outputs a second logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. By doing so, the LLRC compensates for the undesirable effects of gate leakage, and enables the memory to operate effectively and efficiently despite the gate leakage.


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Document History
  • Publication: Apr 7, 2009
  • Application: Jul 2, 2007
    US US 82488307 A
  • Priority: Jul 2, 2007
    US US 82488307 A

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