US 2016/0109870 A1 - Sequential Logic Circuitry With Reduced Dynamic Power Consumption - The Lens

Sequential Logic Circuitry With Reduced Dynamic Power Consumption

Published: Apr 21, 2016
Earliest Priority: Oct 17 2014
Family: 5
Cited Works: 4
Cited by: 3
Cites: 15
Additional Info: Cited Works Full text

Abstract

Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuitry on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.

Claims

Sequential logic circuitry that is configured to record finite logical states for a digital computing system, comprising:
a first latching circuit that is configured to output a first bit;

a second latching circuit that is configured to output a second bit; and

combinational logic circuitry interposed between the first and second latching circuits that is configured to generate the second bit based on at least the first bit, wherein the first and second bits record a given one of two possible finite logical states for the digital computing system.
The sequential logic circuitry defined in claim 1, wherein the first latching circuit comprises a positive level sensitive latching circuit and the second latching circuit comprises a negative level sensitive latching circuit.
The sequential logic circuitry defined in claim 1, wherein the first latching circuit is directly connected to an input of the combinational logic circuitry and the second latching circuit is directly connected to an output of the combinational logic circuitry, wherein the first bit is received at the input of the combinational logic circuitry from an output of the first latching circuit, and wherein the combinational logic circuitry is configured to perform Boolean logical operations on the first bit to generate the second bit.
The sequential logic circuitry defined in claim 1, wherein the first latching circuit comprises a negative level sensitive latching circuit and the second latching circuit comprises a positive level sensitive latching circuit.
The sequential logic circuitry defined in claim 1, wherein the first latching circuit has a first clock input and the second latching circuit has a second clock input, a latch input coupled to an output of the combinational logic circuitry, and a latch output, wherein the first and second clock inputs receive a clocking signal, and wherein the second latching circuit is configured to pass the second bit from the latch input to the latch output when the clocking signal is asserted at a logic high level.
The sequential logic circuitry defined in claim 1, further comprising:
a third latching circuit; and

second combinational logic circuitry interposed between the second latching circuit and the third latching circuit.
The sequential logic circuitry defined in claim 6, further comprising:
a fourth latching circuit;

third combinational logic circuitry interposed between the fourth latching circuit and the third latching circuit, wherein the third combinational logic circuitry receives a third bit and generates a fourth bit based on at least the third bit, wherein the fourth latching circuit is configured to output the fourth bit, and wherein the first, second, third, and fourth bits record a given one of four possible finite logical states for the digital computing system.
The sequential logic circuitry defined in claim 7, wherein the second and fourth latching circuits comprise positive level sensitive latching circuits and the first and third latching circuits comprise negative level sensitive latching circuits.
The sequential logic circuitry defined in claim 1, wherein the combinational logic circuitry comprises a control input that receives control signals from control circuitry, and wherein the combinational logic circuitry is configured to generate the second bit based on the first bit and the control signals received at the control input from the control circuitry.
The sequential logic circuitry defined in claim 1, further comprising:
a first output path coupled to an output of the first latching circuit and configured to convey the first bit to processing circuitry coupled to the sequential logic circuitry; and

a second output path coupled to an output of the second latching circuit and configured to convey the second bit to the processing circuitry, wherein the processing circuitry is configured to combine the first and second bits to identify the given one of the two possible finite logical states that is recorded by the sequential logic circuitry.
An integrated circuit, comprising:
a first latch having a first latch input and a first latch output;

a second latch having a second latch input and a second latch output;

clocking circuitry that provides a clock signal to the first and second latches; and

combinatorial logic circuitry coupled between the first latch output and the second latch input, wherein the first latch is configured to pass a first bit from the first latch input to the first latch output when the clock signal is received at a first logic level, the combinatorial logic circuitry is configured to generate a second bit based on at least the first bit, the second latch is configured to block the second bit from passing to the second latch output when the clock signal is received at the first logic level, and the first and second bits identify only two logical states for a finite state machine on the integrated circuit.
The integrated circuit defined in claim 11, wherein the second latch is configured to pass the second bit from the second latch input to the second latch output when the clock signal is received at a second logic level that is different from the first logic level and wherein the first latch is configured to block the first bit from passing from the first latch input to the first latch output when the clock signal is received at the second logic level.
The integrated circuit defined in claim 11, wherein the first logic level comprises a logic low level and the second logic level comprises a logic high level.
The integrated circuit defined in claim 11, further comprising:
a plurality of processing cores; and

control circuitry, wherein the control circuitry is configured to control the plurality of processing cores to solve a cryptographic puzzle by assigning a plurality of different search spaces to each of the plurality of processing cores, wherein the finite state machine includes the first latch, the second latch, and the combinatorial logic circuitry, wherein the finite state machine is formed in a given one of the plurality of processing cores, and wherein the given one of the plurality of processing cores is configured to solve the cryptographic puzzle using at least the two logical states of the finite state machine.
The integrated circuit defined in claim 14, wherein the control circuitry is configured to control the plurality of processing cores to generate a crypto-currency by solving the cryptographic puzzle, and wherein the plurality of processing cores are configured to solve the cryptographic puzzle by performing Simple Hash Algorithm 265 (SHA-256) hashing operations.
The integrated circuit defined in claim 15, wherein the crypto-currency comprises a Bitcoin crypto-currency.
The integrated circuit defined in claim 14, wherein the control circuitry is configured to provide a control bit to the combinatorial logic circuitry and the combinatorial logic circuitry is configured to generate the second bit by performing Boolean logic operations on the first bit and the control bit.
Finite state machine circuitry configured to record finite logical states of a digital system, comprising:
a first round of latching circuits having first latch inputs and first latch outputs;

a second round of latching circuits having second latch inputs and second latch outputs; and

combinational logic circuitry that receives a first set of bits from the first latch outputs, that generates a second set of bits based on the first set of bits, and that provides the second set of bits to the second latch inputs, wherein the second set of bits records one of two possible finite logical states of the finite state machine circuitry.
The finite state machine circuitry defined in claim 18, further comprising:
additional combinational logic circuitry that receives the second set of bits from the second latch outputs and that has outputs coupled to the first latch inputs, wherein the first and second rounds of latching circuitry are clocked using a clock signal received from clocking circuitry, wherein the first round of latching circuitry is configured to pass the first set of bits from the first latch inputs to the first latch outputs when the clock signal is received at a first logic level, and wherein the second round of latching circuitry is configured to pass the second set of bits from the second latch inputs to the second latch outputs when the clock signal is received at a second logic level that is different from the first logic level.
The finite state machine circuitry defined in claim 19, wherein the additional combinational logic circuitry receives a set of control bits from control circuitry and performs Boolean logic operations based on the received set of control bits and the second set of bits, wherein the second round of latching circuitry comprises a first latch that receives a first bit of the second set of bits and a second latch that receives a second bit of the second set of bits, and wherein the second round of latching circuitry is configured to block the first and second bits from passing from the second set of latch inputs to the second set of latch outputs when the clock signal is received at the first logic level.