Sequential Logic Circuitry With Reduced Dynamic Power Consumption

  • Published: Apr 21, 2016
  • Earliest Priority: Oct 17 2014
  • Family: 5
  • Cited Works: 4
  • Cited by: 3
  • Cites: 15
  • Additional Info: Cited Works Full text
Abstract

Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuitry on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.


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Document History
  • Publication: Apr 21, 2016
  • Application: Aug 28, 2015
    US US 201514839645 A
  • Priority: Aug 28, 2015
    US US 201514839645 A
  • Priority: Oct 17, 2014
    US US 201462065547 P

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